This invention relates generally to power detection circuits and method and, in particular, to methods and circuits for detecting the power in a pulsed signal.
So-called peak detectors have been used to monitor an applied signal power in a circuit. A primary output of the peak detector is a voltage having a magnitude that is related to the power level. However, at low power levels the magnitude of the output voltage is small and, as a result, the output of the peak detector is strongly influenced by any drift in bias potentials, supply voltage, and the detecting device itself (e.g., a diode). The temperature dependance of the detector device alone has been found to have a significant impact on the accuracy of the output voltage.
The problem due to temperature drift has been addressed in the prior art by using an additional temperature dependent device to compensate for the drift of the detector device. The accuracy of the compensation thus relies on a uniformity of the temperature characteristics of the detector device and the compensating device, as well as on a close physical spacing of these two devices in order to avoid any deviation in temperature between the devices.
It has also been observed that the aging of the components may degrade the compensation, and some prior art circuits have thus required testing and tuning.
Reference can be had to U.S. Pat. Nos. 4,523,155, 4,970,456, 5,222,104 and 5,287,555 for teaching various conventional power control circuit arrangements and detectors.
It is thus a first object of this invention to provide an improved method for detecting a power level that is not significantly influenced by drift due to temperature and other disturbances, and to thereby enable an accurate power monitoring or control to be achieved.
It is a further object of this invention to provide circuit embodiments that implement improved power detectors.
The foregoing and other problems are overcome and the objects of the invention are realized by methods and apparatus in accordance with embodiments of this invention.
This invention teaches a method wherein a difference between xe2x80x9coffxe2x80x9d and xe2x80x9conxe2x80x9d states of a pulsed signal is detected so as to provide an accurate indication of the power of the pulsed signal during the xe2x80x9conxe2x80x9d state. It is assumed that during the xe2x80x9coffxe2x80x9d period no significant signal power is present at the input of the detector. It is further assumed that the xe2x80x9conxe2x80x9d period is sufficiently short such that no significant drift occurs during the xe2x80x9conxe2x80x9d period measurement.
Advantages of the invention arise from the fact that the power detection is based on dynamic properties, for example, the peak envelope sensitivity of the detector device. As such, the detected voltage is determined by dynamic properties of the detector device, which are superior to the static properties (e.g., barrier voltage of the detector diode). The detected voltage representative of the power level is not significantly influenced by long term changes in supply voltage, bias potential, or the barrier voltage of the detecting device.
Furthermore, embodiments of this invention allow more freedom in the design of the detector device biasing network, which can be advantageous in order to stabilize the dynamic sensitivity of the detector device at low power levels. The invention can be implemented in such a way that the detected RF power level begins precisely at zero level, which is beneficial in systems using a low supply voltage. In addition, the zero level of the detector output voltage can begin at any desired level if a suitable reference potential (e.g., ground) is available.
The invention can be implemented in a number of ways depending on the type of application. The circuitry used for an analog implementation may be very simple and inexpensive. A digital implementation uses an analog to digital converter and a digital to analog converter and, while being more complex than the analog embodiment, offers the advantages of digital signal processing.
The power detector and transmitter power controller in accordance with this invention eliminates the need to make separate measurements of a reference detector device, and further eliminates the requirement to provide temperature compensation devices for the power detector device.
In accordance with a method of this invention, and circuitry for performing the method, there is disclosed a process for operating a radio frequency (RF) signal power detector. The method includes the steps of (a) sampling the output of an RF detector circuit to obtain a measurement of a value of the output when no RF signal is input to the RF detector circuit; (b) storing the measurement; and (c) subtracting, when an RF signal is input to the RF detector circuit, the stored measurement from the output of the RF detector circuit to provide a subtracted output signal. In pulsed (e.g., TDMA) embodiments of this invention the step of sampling occurs between RF bursts, while in continuous wave (cw) embodiments the step of sampling occurs during a time that the RF signal is prevented from entering the input of the RF detector circuit, such as by opening a connection between an input of the RF detector circuit and a source of the RF signal. A sample and hold function can be provided for sampling and holding the subtracted output signal during a time that the input of the RF detector circuit is opened.
In one embodiment of this invention the step of subtracting includes the steps of combining the measured value with a transmitter power setting signal to obtain a corrected transmitter power setting signal; and subtracting the output of the RF detector circuit, when the RF signal is input to the RF detector circuit, from the corrected transmitter power setting signal.
In one embodiment of a cw circuit there are two RF detector circuits provided in parallel, and the steps of sampling and storing occur in one RF detector circuit simultaneously with the step of subtracting in the other RF detector circuit. In another embodiment a sample and hold circuit is located at the output of a single RF detector circuit, while in a further embodiment a sample and hold circuit is used at the output of a loop amplifier that forms a portion of a closed loop transmitter power control circuit.